1. Field of the Invention
The present invention relates to a pixel clock generation circuit and the method thereof, especially to a circuit and a method thereof that utilize a reference clock inside a chip to generate a pixel clock.
2. Description of Related Art
Please refer to FIG. 1, illustrating a functional block diagram of a prior art circuit that transforms a DisplayPort image signal to a video graphics array (hereinafter referred to as VGA) image signal. The DisplayPort image signal is processed by the clock data recovery (hereinafter referred to as CDR) circuit 110 and a link clock is generated. The decoder 120 decodes the DisplayPort image signal by referring to the link clock and generates data signals. The data signals comprise image data, such as RGB and YUV image data, a control signal and other characteristic signals. The clock generation circuit 130 generates a stable pixel clock and the format generation circuit 140 transforms the image data to VGA image signals according to the pixel clock. As a result, the image signal that originally belongs to the link clock domain is now transformed to an image signal that belongs to the pixel clock domain. The VGA image signals are converted by the Digital-to-Analog converter (hereinafter referred to as DAC) 150 to form analog image signals and are also processed by the horizontal synchronization (hereinafter referred to as Hsync) and vertical synchronization (hereinafter referred to as Vsync) signal generation circuit 160 to generate an Hsync signal and a Vsync signal.
The correctness of the VGA image signals generated by the format generation circuit 140 is highly dependent on the accuracy of the pixel clock. According to the specification of DisplayPort 1.2a, the signals generated by the decoder 120 comprise characteristic signals such as Mvid and Nvid, which can be utilized to find the frequency of the pixel clock by the following equation:fpixelCLK=flinkCLK×(Mvid/Nvid)  (1)fpixelCLK is the frequency of the pixel clock, and flinkCLK is the frequency of the link clock ° Please refer to FIG. 2, illustrating a functional block diagram of the clock generation circuit 130 shown in FIG. 1. The clock generation circuit 130 comprises a reference clock generator 131, a fractional-N synthesizer 136 and a frequency setting circuit 137. The fractional-N synthesizer 136 and the frequency setting circuit 137 are integrated in the video format transformation chip, and the reference clock generator 131 is mounted on the circuit board on which the video format transformation chip installs. The reference clock generator 131 is often implemented by a crystal oscillator, which generates a reference clock with extremely accurate frequency. The fractional-N synthesizer 136 generates the required pixel clock according to the reference clock and a setting value of the frequency setting circuit 137. For example, if the frequency of the reference clock is 25 MHz and the setting value is 4.32, the frequency of the pixel clock generated by the fractional-N synthesizer 136 will be 25M*4.32=108 MHz, which corresponds to a resolution of 1280*960@60 Hz of the VGA image signal; and if the setting value is 4.76, the pixel clock generated by the fractional-N synthesizer 136 will be 25M*4.76=119 MHz, which corresponds to a resolution of 1680*1050@60 Hz of the VGA image signal. The setting value of the frequency setting circuit 137 can be obtained according to the frequency of the reference clock and the frequency of the pixel clock found according to the aforementioned equation (1).
The aforementioned method, however, has some drawbacks. Firstly, the reference clock generator mounted on the circuit board not only increases the overall cost but also is not compatible with the design of miniaturized electronic devices due to the large size of the crystal oscillator. Secondly, the installation of the reference clock generator on the circuit board takes up the circuit board areas and the additional wirings on the circuit board may likely cause electromagnetic interferences. Moreover, the new DisplayPort 1.2 specification supports a multi-stream transport (MST) display technology, which makes the characteristic signals Mvid and Nvid not related to the pixel clock anymore, and therefore the frequency of the pixel clock cannot be found by equation (1). In light of the above drawbacks, the present invention provides different solutions.